Surging electricity requirements tied to artificial intelligence are forcing a rethink of how future computer chips are designed, a senior executive at Taiwan Semiconductor Manufacturing Co (TSMC) said on Thursday. Kevin Zhang, Senior Vice President of Business Development, told reporters at a conference in Amsterdam that customers increasingly demand performance improvements that do not increase power consumption.
"The area customers most want improvement in is energy efficiency. This is true across the board, whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data center," Zhang said, describing a shift in priorities that spans devices from handsets to massive cloud compute farms. Operators, he added, are wrestling with both the cost and the availability of electricity.
The comments underscore a broader turning point for the semiconductor sector. Zhang argued that simply increasing transistor counts on chips is no longer sufficient to meet the needs of AI workloads, which can be particularly demanding in terms of power draw. The industry is therefore placing greater emphasis on design approaches intended to improve energy efficiency while still lifting computational output.
TSMC, the worlds largest contract chipmaker, manufactures AI accelerators for Nvidia and AMD and builds bespoke AI processors for large cloud providers including Google, Amazon, Meta and Microsoft. Zhang said improvements in transistor density remain an important element of TSMCs roadmap, but that other techniques are rising in importance. He highlighted advanced packaging, chip stacking and photonics as ways to boost efficiency by integrating components more closely and reducing energy losses associated with data movement.
He gave a specific projection for the companys technology progression, saying TSMC expects chips based on its forthcoming A14 generation, due around 2028, to reduce power consumption by up to 30% relative to the current N2 technology while delivering more than 20% higher computing performance.
The remarks arrive as competitors also pursue alternative routes to better performance. Chinese firm Huawei this week unveiled a plan it calls the 'Tau Scaling Law,' which focuses on accelerating data movement within chips to improve overall performance. Zhang described the idea as familiar within the industry and said its effectiveness depends heavily on integrating components more tightly, for example through 3D stacking. "The concept has been around in this industry for long enough," he said.
Huaweis approach also reflects constraints facing some Chinese companies, which remain subject to U.S.-led export controls that prevent them from obtaining extreme ultraviolet lithography systems from Dutch manufacturer ASML. Those EUV machines are advanced tools used to print smaller circuits.
TSMC itself is a major purchaser of ASMLs EUV systems. In April, the company said it would postpone adoption of the next generation of EUV technology for several years, a decision Zhang framed in the context of prioritizing design features that improve energy efficiency ahead of pursuing denser circuitry for an upcoming generation of AI chips.
Contextual note: The remarks reflect industry trade-offs between traditional scaling and architectural changes designed to reduce the energy footprint of high-performance computing, particularly for AI workloads. As operators and chipmakers weigh electricity costs and availability, energy efficiency is shaping product roadmaps and equipment deployment plans.