Huawei has outlined a design strategy that prioritizes faster interconnect and lower latency across chip elements rather than relying solely on smaller transistors. The company says this approach - formalised as the Tau Scaling Law and implemented through a technique it calls LogicFolding - could allow Chinese firms to pursue cutting-edge semiconductor performance even as access to the most advanced manufacturing equipment remains constrained.
The shift in emphasis comes against the backdrop of U.S. restrictions that have limited Chinese firms from importing ASML's most advanced extreme ultraviolet - EUV - lithography machines since 2019. That curbs the ability of China-based manufacturers to follow the traditional path of ever-smaller process nodes and to keep pace with global leaders such as Taiwan Semiconductor Manufacturing Company.
For decades the industry has relied on Moore's Law - the empirical observation that the number of transistors on a microchip doubles roughly every two years - to drive improvements in compute density and performance. Huawei is proposing an alternative route that seeks to shorten the time signals take to traverse circuits and entire computing systems, placing time and latency at the heart of performance scaling rather than area alone.
At the centre of Huawei's proposal is LogicFolding, which the company describes as arranging logic, analogue and memory circuits in stacked, more tightly connected structures. Huawei says this configuration could raise density, efficiency and clock speeds over the next decade by reducing the length and delay of critical signal paths, and by enabling more direct coupling between different functional blocks.
He Tingbo, president of Huawei's semiconductor business, set out the rationale this week in Chinese media. "For Huawei, chips face two key constraints. One is inevitable that Moore's Law will hit a physical 'wall' within the next decade," she said. "The other is accidental because of the external restrictions that Huawei encountered this 'wall' earlier than its peers," she added, a likely reference to the import curbs on EUV equipment.
Not everyone sees the new framing as a revolutionary rupture with industry practice. Observers and executives note that reducing latency and stacking dies have long been part of semiconductor innovation. Nvidia chief executive Jensen Huang told reporters in Taipei that while Huawei's announcement might represent a breakthrough for the company, it should not be interpreted as a direct threat to Taiwan Semiconductor. "TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC's technology is very advanced," he said.
The industry has already embraced a range of advanced packaging and 3D stacking techniques to assemble heterogeneous systems. Taiwan Semiconductor's SoIC packaging has been designed to enable tighter integration of heterogeneous chiplets, aiming to reduce area and improve performance. Memory manufacturers such as SK Hynix and Samsung Electronics also employ multi-layer stacking and packaging approaches to increase capacity and efficiency in memory products, which are an important element of AI-focused chips.
Huawei's own technical team argues that LogicFolding goes beyond conventional 3D integrated circuit stacking by "very finely and carefully split[ting] the critical paths of logic circuits across multiple layers," according to Liao Heng, chief scientist at Huawei Semiconductor. The claim is that a more surgical distribution of logic and memory across layers can yield system-level timing improvements rather than purely area-driven gains.
Analysts and vendors caution that stacking layers and driving higher transistor density vertically also concentrate power and heat. Bernstein analysts noted that higher power density raises the risk of overheating, and that production yields and costs will pose additional barriers to wide adoption. These constraints are reflected in Huawei's public roadmap, which acknowledges the need for new design and thermal management approaches.
Huawei has signalled that LogicFolding will require fresh toolchains and methodologies. Executing folded architectures, the company says, calls for electronic design automation - EDA - systems that are optimised for time-based system-level trade-offs rather than traditional area optimisation at the chip level. Handel H. Jones, CEO of International Business Strategies, said during a panel on Tau Scaling that "With the methodology of not optimising the area on a chip level, but on a system level based on time, that will dramatically change the capability requirements for the EDA vendors." Mainstream EDA vendors are central to producing complex blueprints for sophisticated semiconductor devices.
Huawei has provided the most detailed public metrics around a forthcoming Kirin smartphone chip that it says will be the first commercial implementation of the LogicFolding architecture. In a recent speech He said the new Kirin design would improve power efficiency by 41% and raise the chip's peak operating speed by nearly 13% relative to its earlier single-layer design. If these gains are realised at scale, they would be material for handset performance and energy consumption.
Yet Huawei has not disclosed production yields, cost comparisons or detailed benchmarks showing how the Kirin result stacks up against chips produced on more advanced process nodes. That absence of independently verifiable data has prompted caution. Lian Jye Su, chief analyst at Omdia, said there is "nothing concrete that can be independently verified or benchmarked against other players at the moment."
The announcement sketches a potential route for Chinese chipmakers to pursue advanced system performance while constrained on access to the most advanced lithography equipment. At the same time, it exposes a number of technical and commercial uncertainties that will determine whether LogicFolding and Tau Scaling can translate into competitive products at scale, across devices ranging from smartphones to AI data centre processors.
Summary
Huawei has introduced the Tau Scaling Law and LogicFolding, design concepts focused on reducing signal transit time by stacking and tightly linking logic, analogue and memory layers. The strategy aims to maintain progress in chip performance despite limits on access to advanced EUV lithography and the slowing of transistor scaling. Industry participants note the approach builds on existing 3D stacking and advanced packaging, while analysts warn of thermal, yield and tooling challenges. Huawei claims a new Kirin chip will demonstrate these improvements later this year but has not provided independent production or cost data.
Key points
- Huawei promotes time-centric scaling - Tau Scaling Law - and LogicFolding to reduce signal delay by stacking and more tightly connecting circuit layers, aiming to raise density, efficiency and clock speeds over the next decade. (Impacted sectors: semiconductors, smartphone SOCs, AI hardware)
- Industry already employs 3D stacking and advanced packaging - with TSMC's SoIC and multi-layer memory from SK Hynix and Samsung cited - suggesting Huawei's concepts build on existing techniques rather than appearing in isolation. (Impacted sectors: semiconductor manufacturing, advanced packaging suppliers)
- Huawei cites a forthcoming Kirin smartphone chip using LogicFolding with claimed improvements of 41% in power efficiency and nearly 13% in peak speed versus its prior single-layer design, but independent yield and cost data are not provided. (Impacted sectors: mobile devices, consumer electronics)
Risks and uncertainties
- Thermal and power density risks - stacking multiple active layers increases power concentration and the potential for overheating, which can constrain performance and reliability. (Affects: chip design, mobile and data centre deployment)
- Production yield and cost challenges - increased vertical integration can complicate manufacturing and raise costs, limiting commercial viability until yields improve. (Affects: foundry economics, supplier margins)
- Lack of independent verification - Huawei has not released production yield figures, cost comparisons or benchmark data relative to chips on more advanced nodes, leaving claims unverified for now. (Affects: investor and customer confidence across the semiconductor supply chain)