Stock Markets June 11, 2026 09:08 AM

Google Discusses Samsung Production for Memory Die in Next-Gen AI Chip

Deal would use Samsung 2 nm technology for memory I/O die while TSMC maintains compute engine production for Google’s 10th-gen TPU

By Ajmal Hussain
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Google is engaged in talks with Samsung Electronics to have Samsung manufacture a memory input-output die for the company’s upcoming 10th-generation Tensor Processing Unit, code-named Icefish. Under the current plan, Taiwan Semiconductor Manufacturing Co. would continue to produce the chip’s compute engine using its 1.4 nm process while Samsung would supply the component that interfaces with memory. Mass production could begin as early as 2028. Google is collaborating with chip designer MediaTek on the project, and the discussions arise amid reported capacity constraints at TSMC driven by strong demand for AI chips.

Google Discusses Samsung Production for Memory Die in Next-Gen AI Chip
GOOGL TSM
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Key Points

  • Google is in talks with Samsung to produce a memory input-output die for its 10th-generation Tensor Processing Unit, Icefish.
  • TSMC would continue to manufacture the compute engine on its 1.4 nm process while Samsung would use 2 nm technology for the memory interface component.
  • Mass production could begin as early as 2028; Google is collaborating with MediaTek on the project.

Overview

Google is reported to be in negotiations with Samsung Electronics to manufacture a specific component of its next-generation artificial intelligence chip. The discussions focus on having Samsung produce the memory input-output die for Google’s 10th-generation Tensor Processing Unit, which carries the internal code name Icefish.

Technical split in production

According to people familiar with the matter, the current design framework would split manufacturing responsibilities between foundries. Taiwan Semiconductor Manufacturing Co. would remain responsible for the most demanding portion of the TPU - the compute engine - using its 1.4 nanometer process technology. Samsung would be tasked with making the die that links the computing element to memory, using its 2 nanometer production node.

Timeline and partners

Sources indicate the chip could move to mass production as early as 2028. Google is working with Taiwanese chip designer MediaTek on the project. The arrangement represents a notable change from Google’s historical reliance on a single foundry for its chipmaking needs.

Market context

The talks come amid a manufacturing environment in which TSMC is experiencing constrained capacity. That shortage has been attributed to heavy demand for AI chips, particularly from firms supplying data-center accelerators.


Key points

  • Google is negotiating with Samsung to produce a memory I/O die for its 10th-generation TPU, code-named Icefish.
  • Under the present plan, TSMC would continue producing the compute engine on a 1.4 nm node while Samsung would use 2 nm technology for the memory interface component.
  • The chip could enter mass production as early as 2028, and Google is collaborating with MediaTek on the design effort.

Risks and uncertainties

  • Negotiations are ongoing - the final manufacturing arrangement is not confirmed and could change.
  • TSMC’s reported capacity shortages create uncertainty around supply timelines and could affect production pacing.
  • The division of production between multiple foundries introduces integration and supply-chain coordination risks for high-performance chip assembly.

Impacted sectors

The developments touch the semiconductor manufacturing sector, cloud and AI hardware supply chains, and companies providing AI accelerators and data-center computing capacity.

Closing

The discussions mark a potential shift in Google’s chip production approach by engaging multiple foundries to deliver different functional elements of a single AI processor. How the negotiations resolve, and whether production timing holds to the 2028 target, will determine the practical effect on Google’s hardware roadmap and broader foundry demand dynamics.

Risks

  • Negotiations are ongoing and the manufacturing arrangement is not finalized, creating uncertainty around final plans.
  • TSMC’s reported manufacturing capacity constraints could affect timelines and supply of AI chips.
  • Splitting production across multiple foundries may introduce integration and supply-chain coordination risks for high-performance chip assembly.

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