International Business Machines saw its stock climb roughly 5% in premarket trading on Thursday after the company disclosed what it described as a breakthrough in sub-1 nanometer chip technology.
In a company statement, IBM said: "IBM’s new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm chip, unveiled in 2021." The announcement centers on a transistor architecture at the 0.7 nanometer node, which IBM characterized as the first chip technology to function below the 1 nanometer threshold.
The technology relies on what IBM calls a "nanostack" architecture - a three-dimensional arrangement that vertically stacks and staggers transistors. According to the company, this configuration enables the fingernail-sized die to contain nearly 100 billion transistors, representing approximately twice the transistor density of IBM's previously revealed 2 nm chips from 2021.
IBM published technical results alongside the announcement. Those results indicate the new chip is projected to deliver up to 50% more performance or 70% greater energy efficiency when compared with IBM's 2 nm node chips. In addition, IBM presented research at VLSI 2026 showing the nanostack architecture provides 40% scaling in SRAM.
These figures - nearly 100 billion transistors, 0.7 nm node, up to 50% performance improvement, 70% energy-efficiency gain, and 40% SRAM scaling - are the specific claims IBM has released in connection with the nanostack design and its sub-1 nm chip work.
Key takeaways
- IBM announced a sub-1 nm transistor architecture at the 0.7 nanometer node and described a three-dimensional "nanostack" that stacks and staggers transistors.
- The company stated the new chip places nearly 100 billion transistors on a fingernail-sized die - roughly double the density of IBM's 2 nm chip unveiled in 2021, and reported projected gains of up to 50% performance or 70% improved energy efficiency relative to its 2 nm node chips.
- Research presented at VLSI 2026 showed the nanostack architecture delivers 40% scaling in SRAM. Sectors tied most directly to this development include semiconductor manufacturing and computing hardware.
Risks and uncertainties
- The performance and energy-efficiency figures are presented as projections; real-world production results or commercial implementation are not detailed in the announcement.
- The announcement provides technical results and research findings but does not specify commercialization timelines or manufacturing readiness, leaving uncertainty about market deployment.
- Scaling research such as the 40% SRAM improvement was presented at an academic and industry forum (VLSI 2026), which documents research progress but does not guarantee immediate transfer to mass production. These uncertainties affect semiconductor manufacturing and computing hardware markets.
While IBM's statement frames the 0.7 nm nanostack as a technical milestone, the company-provided figures and the presentation at VLSI 2026 leave open questions about the path from demonstrated research to broad commercial availability. The stock market reacted in premarket trading, reflecting investor attention to the announced engineering progress.