Stock Markets March 11, 2026

Synopsys unveils integrated engineering-aware software for AI chip design

New toolset aims to fold mechanical and thermal analysis into the chip design workflow following Ansys buyout

By Nina Shah SNPS AMD NVDA INTC
Synopsys unveils integrated engineering-aware software for AI chip design
SNPS AMD NVDA INTC

Synopsys introduced a suite of software tools to address the growing complexity of artificial intelligence chip design, embedding engineering analyses into earlier design stages. The release - the first major offering since its $35 billion acquisition of engineering software company Ansys - targets challenges created by the shift to multi-chiplet architectures and the resulting thermal and mechanical stresses.

Key Points

  • Synopsys launched new software tools to address the growing complexity of AI chip design, debuting them at a Silicon Valley conference.
  • The product rollout is the first major set of offerings since Synopsys' $35 billion purchase of engineering software firm Ansys, aimed at integrating mechanical and thermal analyses into chip design.
  • The shift from single monolithic chips to packaged assemblies of smaller "chiplets" creates new thermal and mechanical challenges for semiconductor makers and their design-tool providers.

SANTA CLARA, California, March 11 - Synopsys on Wednesday introduced a set of software tools intended to help designers manage the rising complexity of creating artificial intelligence chips. The launch represents the initial wave of new offerings following Synopsys' $35 billion acquisition of engineering software firm Ansys.

For decades Synopsys has been a principal supplier of electronic design automation software used to determine how to place and connect the tens of billions of transistors inside chips made by companies such as Advanced Micro Devices and Nvidia, the latter of which last year invested $2 billion in Synopsys. The company announced the new tools at a conference in Silicon Valley.

Synopsys said the products respond to an industry-wide shift away from monolithic chips toward designs composed of many smaller "chiplets" that are stacked and packaged together in increasingly intricate configurations. That architectural trend was a key driver of the Ansys deal, Synopsys executives said, because designers must now confront issues historically handled by mechanical engineers.

Those issues include whether heat generated by a chiplet could cause it to warp or expand in ways that might cause cracking or separation from an adjacent chiplet - a failure that could destroy a complex chip assembly with a manufacturing cost that can run into the tens of thousands of dollars.

Sassine Ghazi, the chief executive officer of Synopsys, described the new tools as an effort to incorporate those engineering analyses into the tools chip designers already use. "Typically you have engineers designing for each step in a siloed way," Ghazi said. "What ends up happening is that the product is more expensive and its not operating at its maximum potential. Were putting them in the design phase, so youre able to achieve a better performance, lower power and definitely lower cost."

The company said these capabilities are being embedded into the design flow used by chipmakers such as Intel and other industry participants. By integrating mechanical and thermal considerations earlier in the design process, Synopsys aims to reduce downstream surprises and the need for costly redesigns or rework.

Synopsys' announcement underscores the increasing overlap between electronic design automation and traditional engineering disciplines as chip architectures become more heterogeneous and physically complex. The new tools are positioned as the first tranche of products to emerge following the Ansys acquisition, reflecting an attempt to bridge those engineering domains within a single set of software solutions.


Impacted sectors: Semiconductor design, electronic design automation (EDA) software, and engineering simulation tools.

Risks

  • Thermal and mechanical stresses on chiplets - such as warping, expansion, cracking or separation - can destroy complex, high-cost chip assemblies, posing supply and production risks for semiconductor manufacturers.
  • Siloed engineering workflows that delay mechanical and thermal analysis until later stages can increase product costs and reduce operating performance, potentially leading to costly redesigns.
  • Integrating traditionally separate engineering analyses into the chip design flow may present execution and adoption challenges for tool providers and chipmakers, affecting timelines in semiconductor and EDA sectors.

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