Stock Markets March 11, 2026

Navitas Semiconductor Shares Rally After Launch of Two 1200 V SiC MOSFET Packages

New QDPAK and low-profile TO-247-4L packages based on 5th generation GeneSiC technology aim at AI data centers and energy infrastructure

By Priya Menon NVTS
Navitas Semiconductor Shares Rally After Launch of Two 1200 V SiC MOSFET Packages
NVTS

Navitas Semiconductor (NASDAQ: NVTS) stock climbed 20% after the company unveiled two new silicon carbide MOSFET packages built on its 5th generation GeneSiC Trench-Assisted Planar SiC MOSFET platform. Both packages carry 1200 V ratings and are intended for high-power density uses in AI data centers and energy infrastructure, offering claimed improvements in key device figures of merit and design features that address thermal management and height-constrained environments.

Key Points

  • Navitas launched two 1200 V SiC MOSFET packages - a top-side cooled QDPAK and a low-profile TO-247-4-LP - aimed at AI data centers and energy infrastructure.
  • The 5th generation GeneSiC platform claims a 35% improvement in RDS,ON × QGD figure of merit and about a 25% improvement in QGD/QGS ratio, with a threshold voltage above 3 V to prevent parasitic turn-on.
  • Four initial devices are available with on-resistance values between 6.5 mΩ and 12 mΩ; both packages support these devices, addressing thermal management and height-constrained designs.

Navitas Semiconductor's shares surged 20% after the company introduced two new silicon carbide (SiC) MOSFET packages targeted at high-power density applications in AI data centers and energy infrastructure. The products are built on the company's 5th generation GeneSiC Trench-Assisted Planar SiC MOSFET technology platform and both carry 1200 V voltage ratings.

The new offerings include a top-side cooled QDPAK and a low-profile TO-247-4-LP. The QDPAK is designed to dissipate heat through the package top and occupies a 15 mm x 21 mm footprint with a height of 2.3 mm. That design supports applications up to 1000 VRMS and incorporates a 5 mm creepage distance.

The TO-247-4-LP variant delivers a reduced vertical profile for environments where height is constrained, specifically noting AI data center power supplies as a target application. This package also employs asymmetrical leads to improve manufacturing tolerances.

Navitas said the 5th generation GeneSiC platform delivers a 35% improvement in the RDS,ON × QGD figure of merit and roughly a 25% improvement in the QGD/QGS ratio compared with prior generations. The technology also uses a threshold voltage greater than 3 V to mitigate parasitic turn-on risk.

The initial product set comprises four devices, all rated at 1200 V, with on-resistance values spanning 6.5 mΩ to 12 mΩ. Each device will be offered in both the QDPAK and TO-247-4-LP packages.

Paul Wheeler, vice president and general manager of Navitas's SiC business unit, said the new package designs are a response to customer demand for increased power density in limited space. The company positioned the QDPAK toward applications benefiting from top-side cooling and the low-profile TO-247-4-LP toward use cases where vertical space is constrained.

The product specifications and packaging choices emphasize thermal management, high-voltage capability and manufacturability for high-power applications in data center and energy infrastructure segments. Market reaction to the announcement was immediate, with NVTS shares rising 20% on the news.


Additional context and considerations

  • The technology improvements cited focus on RDS,ON × QGD and QGD/QGS ratios, as well as an elevated threshold voltage to prevent parasitic turn-on.
  • The QDPAK's top-side cooling and the TO-247-4-LP's reduced vertical footprint are positioned to address thermal and height constraints, respectively.
  • The initial four products cover on-resistance values from 6.5 mΩ to 12 mΩ, all at 1200 V, and are available in both announced packages.

Risks

  • Performance and manufacturability outcomes - while the company reports specific improvements in figures of merit and lead design changes to improve manufacturing tolerances, actual production yields and real-world performance are not detailed in the announcement (impacts semiconductors and manufacturing).
  • Thermal and voltage system integration - the QDPAK and TO-247-4-LP are designed for specific thermal and height constraints, but integrating them into existing AI data center or energy infrastructure power systems may present engineering challenges not covered in the release (impacts data center power supplies and energy infrastructure).

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